WholeAustin · Austin metro · Semiconductors
The complete Austin guide to semiconductors — the local businesses and the firms that shape the market, each read for how findable it is online, alongside the concepts, the news and the questions that define the field. Own one? See where you stand and exactly what to improve.
The firms, funds and institutions that set the terms in semiconductors — context, not local listings; never scored.
What a node name actually means, planar to FinFET to gate-all-around, the transition to backside power delivery, and why leading edge matters for some products and is irrelevant for others. The pillar that separates informed content from press-release paraphrase.
Cleanroom flow, lithography-etch-deposition cycles, metrology and inspection, defect density and D0 models, learning curves, cycle time and fab utilisation, and the economics of a plant whose cost is almost entirely fixed.
2.5D interposers, 3D stacking and hybrid bonding, CoWoS and its equivalents, chiplets, substrates and OSAT capacity. Now the binding constraint on AI silicon and the highest-value topic in the cluster.
Specification through RTL, synthesis, place and route, timing closure, DFT, physical verification and tape-out — plus PDKs, IP licensing and what a design team actually buys. The pillar that reaches design engineers rather than executives.
Lithography, etch, deposition, CMP, implant, test and inspection tooling, plus wafers, photoresists, gases, CMP slurries and filtration. Concentrated supply, long lead times and a handful of genuine single points of failure.
Memory as its own commodity cycle with its own capex logic, and HBM as the piece of it that AI accelerators cannot ship without. Stack heights, bandwidth, qualification cycles and the crowding-out of conventional DRAM capacity.
GPUs, custom accelerators, networking silicon and the rack-level system they sit in. Where leading-edge wafer demand, HBM demand and advanced-packaging demand all originate, and how hyperscaler custom silicon changes the buyer set.
MCUs, power devices, sensors and analog for vehicles and factories, with their own qualification regime — AEC-Q100, ISO 26262, PPAP, ten-to-fifteen-year longevity commitments — and their own inventory cycle that runs out of phase with AI.
The long-lived, mature-node, high-margin part of the industry: power management, signal chain, GaN and SiC, RF front ends. Design skill and process recipes matter more than node size, and product lifecycles run for decades.
Microcontrollers, wireless SoCs and ultra-low-power silicon for connected products, plus the toolchains and reference designs that decide the socket. The segment where Austin companies compete directly and globally.
Who owns which asset, how gross margin structure differs across the models, why capex intensity and utilisation drive foundry economics, and how allocation and long-term supply agreements reshape the buyer-supplier relationship.
Lead times, allocation, double ordering, the bullwhip effect, distributor and broker channels, last-time-buy and end-of-life notices, second sourcing and the qualification cost of switching parts.
The CHIPS and Science Act and its award and clawback conditions, the advanced manufacturing investment credit, state-level programmes including the Texas CHIPS Act, export controls and the Entity List, tariffs and Section 232, and the compliance load these place on ordinary commercial teams.
Who is actually here and doing what — Samsung's Austin fabs and Taylor site, NXP's largest US campus, AMD's largest US site, Silicon Labs and Ambiq headquarters, Applied Materials and Tokyo Electron operations, the Texas Institute for Electronics packaging effort, and the state programmes funding it.
Technician, operator, equipment-engineer and process-engineer roles, community-college and university pathways, apprenticeship and certificate programmes, relocation and retention, and the honest arithmetic of staffing a new fab in a metro that is already tight.
Fab electricity and interconnection queues, water withdrawal and reclaim rates, ultrapure water, abatement of process gases, PFAS and chemical substitution, and the scope-3 reporting large customers now demand from suppliers.
foundry manufactures wafers for others, IDM designs and manufactures its own products, fabless designs and outsources manufacturing -- and note the lines blur now that IDMs sell foundry services
say plainly that node names stopped corresponding to any physical dimension years ago and are marketing labels for a generation; compare density, performance and power from the vendor's own disclosures instead
outsourced semiconductor assembly and test -- the companies that package the die and test the finished part; note that advanced packaging has made this layer strategically important rather than a commodity back end
explain good die per wafer against total die, the relationship to defect density and die size, and why a large die is punished twice -- fewer die per wafer and lower yield on each
describe packaging as the step that connects multiple die and memory stacks at high bandwidth, and CoWoS as the interposer-based family that AI accelerators depend on -- which is why packaging capacity, not wafer capacity, has been the bottleneck
a chiplet splits what would have been one monolithic die into several, each on the node that suits it, connected in package -- it improves yield and mixes process technologies at the cost of packaging complexity
describe it as the die-to-die interconnect standard that would make a merchant chiplet market possible, note it has advanced through successive revisions, and be honest that multi-vendor interoperability is still ahead of the ecosystem
high bandwidth memory stacks DRAM die vertically next to the processor; it consumes far more wafer area and packaging effort per bit than standard DRAM, so shifting capacity to HBM tightens ordinary DRAM too
extreme ultraviolet patterning at 13.5nm wavelength; High-NA raises numerical aperture for finer features at the cost of a smaller printed field, which forces mask and design-partitioning changes
tape-out is releasing the final design for mask making; NRE is the one-time engineering and mask-set cost before a single sellable part exists -- and it rises sharply at leading-edge nodes
the process design kit encodes the foundry's device models and rules; a port means re-characterization, re-verification and often re-layout, which is why second-sourcing at the leading edge is rare
describe the stress-test qualification grades by temperature, and connect it to ISO 26262 functional safety and PPAP -- the calendar time is the qualification and the customer's own validation, not the silicon
explain that lead times diverged by segment -- leading-edge AI parts and their packaging and HBM allocated far out, while mature-node analog, MCU and power parts came down through the inventory correction -- and say the only reliable number is the current quote from the supplier or franchised distributor for your specific part
explain the out-of-phase cycles -- customers over-ordered mature-node parts during the shortage and then destocked through 2023-2025 while AI demand hit packaging and memory capacity -- and note the 2026 state: the broad correction has worked through, with residual tightness now concentrated in silicon carbide MOSFETs, safety-rated 32-bit MCUs and IGBT modules
describe allocation as the supplier rationing constrained capacity by customer, and LTAs as volume and price commitments that buy priority -- and name the risk honestly, that a take-or-pay commitment becomes a liability when demand turns
frame it on volume against NRE, power and performance requirements, expected product life and supply security; the crossover depends on the reader's volume and mask cost quote, which is not public
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